1. Field of the Invention
This invention relates to processors and, more particularly, to implementation of memory systems.
2. Description of the Related Art
To improve execution performance, processors commonly include caches. In particular, processors may include writeback caches, which may be configured to write modified data to a lower level of the memory hierarchy when the modified data is evicted from the cache, rather than when the data is modified.
Because the access latency of lower levels of a memory hierarchy may be longer than the latency of the writeback cache, evicted data may be buffered before it is written to the lower level memory. However, if buffer capacity is reached, operation of the writeback cache may stall until the lower level memory makes progress, which may negatively affect processor performance. Increasing the data storage capacity of the buffer may help to reduce the likelihood and/or duration of stalling. However, the physical design implications of increasing buffer capacity, such as routing, die size, and power consumption considerations, may render this option impractical, especially in multicore processor designs where buffers may be replicated across many processor cores.